1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory (SRAM) having an improved read operation margin and speed.
2. Description of the Related Art
A typical SRAM is comprised of a plurality of word lines, a plurality of pairs of bit lines, a plurality of static memory cells connected at intersections between the word lines and the pair of bit lines, and at least one sense amplifier for sensing a difference in potential between a selected pair of bit lines. Also, one resistive load is connected to each bit line, so as to generate the above-mentioned difference in potential between the selected pair of bit lines. That is, when one word line is selected, currents flow from the resistive loads into the memory cells connected to the selected word line, to generate a difference in potential between each of the pairs of bit lines. In this case, the potentials at the bit lines generated from the memory cells are propagated via the corresponding bit lines per se to the sense amplifier. Simultaneously, one of the pairs of bit lines is selected, i.e., one memory cell is selected, to complete a read operation for one selected memory cell. Thus, the read operation is dependent upon the resistance of the bit lines, since currents from the resistive loads flow via the bit lines to the memory cells.
In a prior art SRAM, however, a row of resistive loads are connected at bit line locations far away from the sense amplifier. As a result, when a selected memory is far away from the resistive loads, i.e., close to the sense amplifier, an unnecessary large reduction in potential is generated in the bit lines due to the long length of the bit lines between the resistive loads and the selected memory cell. As a result, the difference in potential between the pair of bit lines connected to the selected memory device is quite large, thus deteriorating the read operation margin. Also, this large difference in potential decreases the read-operation speed. This will be explained later in detail.
Also, in another prior art SRAM, a row of resistive loads are connected at locations on the bit lines close to the sense amplifier. As a result, when a selected memory is far away from the resistive loads, i.e., far way from the sense amplifier, the speed of a read operation is very low due to the long length of the bit lines between the resistive loads and the selected memory cell. This will be explained later in detail.
Particularly, recently, as the integration of SRAM's has advanced, the length of bit lines has been increased while the width of bit lines has been decreased. This further decreases the read operation speed and further deteriorates the read operation margin.